Senior Design Verification Engineer - Interconnect IP

The FBHUB (Frame Buffer HUB) Shanghai team focuses on memory subsystem IP design and verification, contributing to FBHUB RTL development, verification infrastructure, coverage analysis, and performance validation. We collaborate closely with the Santa Clara FBHUB team to drive quality assurance and accelerate project execution across multiple GPU roadmap milestones. Our work encompasses verification methodology development, regression management, and design validation, with a commitment to deliv…